* Intel Corporation (Semiconductors): Understanding of standard cell architecture , Design of standard cell layouts for newest process technologies, Optimization of standard cell layouts considering area/performance/reliability trade-offs.Verification of layouts for design and architecture rules, implementation of DFM and ESD guidelines. recognize failure prone layout structures and produce robust layouts
Equivalence verification of layouts with respect to schematics
Development of automation for library design, quality checking and reliability verification, Exploration of standard cell library architecture with optimal placement and routing, Release verification.
Improving new automation systems with TCL & PERL scripting.