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Rtl/Tb Development in Verilog / System Verilog

Published on the September 16, 2020 in IT & Programming

About this project

USD 1,000 - 3,000

We are building high performance IPs that can fit inside a variety of ASICs ranging from low power IoT ASIC to higher performance Desktop/Server ASICs.  The work centers around some of the interesting and critical areas of modern computer design such as  Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc. 

The work is in an advanced prototype stage and we plan to launch fully as a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.

We are looking for engineers who can micro-arch, code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Architecture Spec. The engineering need to have - excellent/good Verilog/SystemVerilog/Perl Skillset (with Make, Python, Bash skillset an added advantage). The basic coding will be Perl mixed Verilog/SV and make/bash based build system.

We are looking for people with good energy, passion for rtl/tb coding , attention to detail and willingness to learn and solve tough problems. 
Persons with the above skillset can apply. Freshers/junior engineers who are willing to learn sincerely, are welcome. Engineers looking for an opportunity to explore in-depth ASIC design are welcome as well.

The work can be done with small deliverable model or continuous engagement model.

Adding a placeholder time/money here. Details can be discussed.

Project overview

Verilog or System Verilog Based RTL and TB Development for ASIC IP Design

Category IT & Programming
Subcategory Other
Project size Medium
Is this a project or a position? Project
I currently have I have specifications
Required availability As needed

Deadline: Not specified

Skills needed


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