The work is in an advanced prototype stage and we plan to launch fully as a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.
We are looking for engineers who can micro-arch, code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Architecture Spec. The engineering need to have - excellent/good Verilog/SystemVerilog/Perl Skillset (with Make, Python, Bash skillset an added advantage). The basic coding will be Perl mixed Verilog/SV and make/bash based build system.
We are looking for people with good energy, passion for rtl/tb coding , attention to detail and willingness to learn and solve tough problems.
Persons with the above skillset can apply. Freshers/junior engineers who are willing to learn sincerely, are welcome. Engineers looking for an opportunity to explore in-depth ASIC design are welcome as well.
The work can be done with small deliverable model or continuous engagement model.
Adding a placeholder time/money here. Details can be discussed.
Verilog or System Verilog Based RTL and TB Development for ASIC IP Design
Category IT & Programming
Project size Medium
Is this a project or a position? Project
I currently have I have specifications
Required availability As needed
Deadline: Not specified