Design a Behavioral implementation for an Alu

Design a behavioral implementation for an alu as explained below:
i. The alu has four inputs: two 6-bit signed values, a carry-in and a 4-bit control signal that determines which operation the alu should perform. The ALU has a single 12-bit signed output (plus a carry-out for the adder) which is the result of the operation.


The ALU can perform sixteen (16) operations as per the table below.
II. The ALU should instantiate a single 6-bit adder (also used for subtract), a left/right shifter as well as a 6-bit multiplier.

It should also instantiate the 4 logic functions of not, or, and and exor.
III. The simplest approach is to design each module for each instruction separately and use an appropriate test bench for each module.

All completed modules can then be integrated into a final module for the ALU. Use the case statement in Verilog to specify the 16 ALU functions.
IV.

Simulate the ALU outputs in Quartus and show the final result (i.e. 12-bit outputs including carry-out) using the four 7-segment LEDs (in hexadecimal format) in the DE2- 115 Altera FPGA board. Use the 17 switches on the board for the A,B,S and Cin inputs. Use the single bit LED lights (red and green) to indicate the corresponding state of the 17 switches respectively.


The report must include the following:
1. The background theory of the arithmetic and logic unit (alu) and how the alu can be linked to other functional units in the cpu.
2. The full listing of the Verilog programs describing the design of the ALU.
3. The test bench file used to test all the functionalities (i.e. Test all 10 instructions) of the designed
ALU.
4. The waveform diagrams of the signals described in the test bench.
5. The graphics demonstration of the outputs on the de-2 fpga board.